1. Field of the Invention
The present invention relates to the technical field of semiconductor devices, and in particular to the structure of surge protective component.
2. Description of Related Art
In the related art, two terminal surge protective components are widely used as semiconductor devices for protecting electronic circuits from surge voltages occurring due to lightening strikes, etc.
Numeral 101 in FIG. 8 is an example of a semiconductor device of the related art. Here, P-type base layers 113a and 113b are provided at a portion in the vicinity of both the inner side surface and the reverse side surface of an N-type substrate 109 so that a PN junction is formed between the substrate 109 and the base layers 113a and 113b. 
The base layers 113a and 113b are positioned substantially in the vicinity of the center of the semiconductor device 101, and are patterned so as to be rectangular in shape, with rounded corners. N-type emitters 122a and 122b are arranged at a part in the vicinity of the surface of the inside of the base layers 113a and 113b so that a PN junction is formed between each of the emitter layers 122a and 122b and the base layers 113a and 113b. 
Ohmic layers 121a and 121b with a high P-type surface concentration are provided at a portion where the emitter layers 122a and 122b provided in the vicinity of the surface on the inside of the base layers 113a and 113b are not provided.
Metal films 127a and 127b are formed at the surfaces of the emitter layers 122a and 122b and the ohmic layers 121a and 121b on the surface side and rear surface side of the substrate 109.The metal film 127a at the surface side is electrically connected to the surface side emitter layer 122a and the ohmic layer 121a, but is not connected to the substrate 109. The metal film 127b of the rear surface side is electrically connected to the surface side emitter layer 122b and the ohmic layer 121b, but is not connected to the substrate 109.
The semiconductor device 101 of this structure has a four-layer PNPN structure when viewed from the surface side or from the rear side. This means that the PN junction between the base layers 113a and 113b and the substrate 109 is reverse biased for whichever of the metal films 127a and 127b a voltage is applied to, wherein a current flows as a result of this PN junction experiencing an avalanche breakdown.
When a current flows, the PNPN structure latches up, and a voltage state lower than a voltage during avalanche breakdown is maintained between the metal films 127a and 127b. Therefore, when the semiconductor device 101 is connected in parallel with an electronic circuit, when a surge voltage is applied to the electronic circuit, the semiconductor device 101 conducts in such a manner that the surge voltage is not applied to the electronic circuit.
There are, however, drawbacks with this semiconductor device 101 in that the PN junction formed between the base layers 113a and 113b and the substrate 109 are easily destroyed and reliability therefore becomes poor.
In order to improve the reliability of the semiconductor device 101, there has been proposed a structure where a high-concentration N-type layer is provided within the substrate 110 so that a PN junction is formed between the N-type layer and base layers 113a and 113b. However, this requires a complex process because the N-type layer is buried more deeply than the base layers 113a and 113b. 
As the present invention sets out to resolve the problems encountered in the related art, it is the object of the present invention to provide a surge protection semiconductor device that has a straightforward manufacturing process, a simple structure, and is highly reliable.
In order to resolve the aforementioned problems, a semiconductor device of the present invention having, when one of either an N-type or P-type is defined as a first conductivity type, and the other is defined as a second conductivity type, a semiconductor substrate of the first conductivity type, comprises first and second buried layers (in this invention, a buried layer may include a layer being partially exposed on the surface of a semiconductor substrate 9 as shown in FIG. 6) provided within the semiconductor substrate, being of the first conductivity type, and being of a higher concentration than the semiconductor substrate, first and second emitter layers of the first conductivity type, first and second base layers of the second conductivity type, and a substrate layer constituted by the semiconductor substrate. The substrate layer is sandwiched between the first and second buried layers. At least a part of the first and second base layers are positioned on one side surface and the other side surface of the semiconductor substrate so as to form PN junctions with the first and second buried layers. At least a part of the first and second emitter layers are located in a vicinity of a surface inside of the first and second base layers so as to form PN junctions with the first and second base layers.
The first and second base layers are respectively provided between the first and second emitter layers and the first and second buried layers, and the first and second buried layers are located between the first and second base layers and the substrate layer.
With this semiconductor device of the present invention, the first and second metal films are formed on both sides of the semiconductor substrate, the first emitter layer and the first base layer are electrically short-circuited by the first metal film; and the second emitter layer and the second base layer are electrically short-circuited by the second metal film.
Further, with the semiconductor device of this invention, ring-shaped first and second moats with bottom surfaces reaching the buried layers are formed on both sides of the semiconductor substrate and the first and second emitter layers are located on inside of the first and second moats.
The insides of the first and second moats of this semiconductor device of the present invention are filled with oxide.
Moreover, at least a part of the first and second base layers are positioned at a region on outside of the first and second moats of surfaces of the semiconductor substrate.
Still further, at least a part of the first and second buried layers are positioned at a region on the outside of the first and second moats of the surfaces of the semiconductor substrate of the semiconductor device of the present invention.
A semiconductor device manufacturing method of the present invention comprises the steps of, when one of an N-type and P-type is defined as a first conductivity type and the other is defined as a second conductivity type:
forming a first buried layer of the first conductivity type in the vicinity of the surface at the inside of one side of the semiconductor substrate of the first conductivity type and forming a second buried layer of the first conductivity type in a vicinity of the surface of the other side, in such a manner that the first and second buried layers sandwich a substrate layer composed of a remaining portion of the semiconductor substrate, forming first and second base layers of the second conductivity type in the vicinity of surfaces at insides of the first and second buried layers in such a manner that bottom surfaces are positioned in the first and second buried layers; and forming first and second emitter layers of the first conductivity type in the vicinity of surfaces at insides of the first and second base layers so that the bottom surfaces thereof are positioned in the first and second base layers.
In the semiconductor device manufacturing method of the present invention, the first and second buried layers are formed by introducing an impurity of the first conductivity type into the semiconductor substrate with the surfaces of both sides of the semiconductor substrate completely exposed and diffusing impurity of the first conductivity type.
Further, in the semiconductor device manufacturing method of the present invention, the first and second base layers are formed by introducing an impurity of the second conductivity type into the first and second buried layers with the surfaces of the first and second buried layers completely exposed and diffusing impurity of the second conductivity type.
Moreover, the semiconductor device manufacturing method of the present invention further comprises a step of, with ring-shaped moats having bottom surfaces reaching positions deeper than the bottom surfaces of the base layers, forming moats including the first and second emitter layers inside of the ring-shaped moats on both sides of the semiconductor substrate.
Further, the semiconductor device manufacturing method of the present invention may comprise a further step of forming first and second metal films short-circuiting the first and second emitter layers positioned inside of the ring-shaped moats and the first and second base layers after filling the insides of the first and second moats with oxide and forming first and second passivation films.